Exemplary embodiments of the present invention relate to a phase locked loop and method for operating the same, and more particularly, to a phase locked loop (PLL) which synchronize a reference clock with a feedback clock and method for operating the same.
Semiconductor devices such as double data rate (DDR) synchronous dynamic random access memory (SDRAM) receive an external clock as a reference to match operation timings.
However, since a clock skew may occur in the external clock due to the delay in clock/data path of internal circuits, an internal clock is desired to be synchronized with the external clock by inversely compensating for the internal clock so that the internal clock which is delayed through internal circuits is aligned to a center or an edge of the external clock.
In order to synchronize the internal clock with the external clock, a clock synchronization circuit is provided in the semiconductor device. Examples of the clock synchronization circuit include a phase locked loop (PLL) and a delay locked loop (DLL).
The PLL having a frequency multiplication function is mainly used when the frequency of the external clock is different from the frequency of the internal clock, and the DLL is mainly used when the frequency of the external clock is equal to the frequency of the internal clock.
The configuration of the PLL is basically similar to that of the DLL. The PLL uses a voltage controlled oscillator (VCO) to generate the internal clock while the DLL uses a voltage controlled delay line (VCDL).
In particular, the PLL is used in a variety of applications, e.g., communications, wireless systems, digital circuits, etc, generates various clocks through frequency synthesis and easily achieves a clock data recovery (CDR).
The PLL includes a phase frequency detector (PFD) for detecting a phase difference between a reference clock and a feedback clock and matches a phase of the reference clock with a phase of the feedback clock by driving a charge pump in accordance with the detected phase difference of the PFD and varying a control voltage of a voltage controlled oscillator.
However, even if the phase of the reference clock is matched with the phase of the feedback clock, because the PLL has a charge pump having less than ideal characteristics, a phase offset having a direct current (DC) component still occurs between the reference clock and the feedback clock, for example, by a mismatching of an up current and a down current in the charge pump.
While the phase of the reference clock is desired to be matched with the phase of an output clock (feedback clock) outputted from the PLL when the PLL is turned on, a phase offset still exists between the reference clock and the feedback clock, and thus, the efficiency of the PLL decreases.
Moreover, since a control voltage level of a voltage controlled oscillator included in the PLL is varied according to a change of a process/voltage/temperature (PVT) and an input frequency, a current driving power of a transistor is varied according to a change of the PVT, and the phase offset having a DC component may be varied according to an operating condition of the PLL.